Challenges of Scaling and Integration in VLSIReview of Fabrication Processes
MOS Devices and scaling challenges
Short channel effects, hot carrier effects, gate dielectrics, gate electrodes, junction-contact integrationCMOS process integration
Well technology for CMOS, isolation, latchup in CMOS, drain and channel engineering, stress effects and mobility enhancement, metal gate electrodes, high k - dielectricsBipolar Process Integration
Bipolar transistors: polysilicon E, self aligned structures, SiGe BJTsIsolation technologies for ICs and SOI devices
Shallow trench isolation, SOI devices: wafer bonding, SIMOX, and selective or lateral growth of epitaxial layersSilicon bipolar and BICMOS technologies
Applications in RF and mixed-signal circuitsSemiconductor memories
RAM and ROM, SRAM, DRAM, EPROM, FLAHInternational Roadmap for Semiconductors (ITRS) requirements; short and long term challenges in fabrication of:
logic circuits, DRAM, and non-volatile memoriesITRS requirements; short and long term challenges solved by:
emerging devices and emerging materialsBack End processes; Multilayer Interconnect technology for VLSI
Conductors, dielectrics, planarizationYield and reliability issues
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