ELEE 7366

Syllabus for Spring 2017

 

Challenges of Scaling and Integration in VLSI

Review of Fabrication Processes

MOS Devices and scaling challenges

Short channel effects, hot carrier effects, gate dielectrics, gate electrodes, junction-contact integration

CMOS process integration

Well technology for CMOS, isolation, latchup in CMOS, drain and channel engineering, stress effects and mobility enhancement, metal gate electrodes, high k - dielectrics

Bipolar Process Integration

Bipolar transistors: polysilicon E, self aligned structures, SiGe BJTs

Isolation technologies for ICs and SOI devices

Shallow trench isolation, SOI devices: wafer bonding, SIMOX, and selective or lateral growth of epitaxial layers

Silicon bipolar and BICMOS technologies

Applications in RF and mixed-signal circuits

Semiconductor memories

RAM and ROM, SRAM, DRAM, EPROM, FLAH

International Roadmap for Semiconductors (ITRS) requirements; short and long term challenges in fabrication of:

logic circuits, DRAM, and non-volatile memories

ITRS requirements; short and long term challenges solved by:

emerging devices and emerging materials

Back End processes; Multilayer Interconnect technology for VLSI

Conductors, dielectrics, planarization

Yield and reliability issues

 

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Students' presentations

Final Exam